The present invention related to the field of integrated circuit devices, and in particular to output circuits for such devices.
Many integrated circuit devices are characterized by one or more output terminals which provide device output signals which drive other components of the particular system in which the integrated circuit is installed. Output buffer signal transitions generate large current changes, which can result in voltage variations on supply pins. Inductance present in packages and boards results in on-die power supply oscillations and glitches. These supply variations can cause functional failures and access time push outs.
A difficult noise/speed tradeoff occurs due to manufacturing process variations, supply and temperature variation. On extreme process, supply and temperature corners, output drive current can vary by well over 200%. This results in significant noise in the fast process corner, with slow output transitions in the slow process corner.
It is known to provide compensation for process variations and the effects of temperature variation in output buffer circuits. Circuits which provide such compensation in an output buffer circuit are described in U.S. Pat. No. 4,723,108, assigned to a common assignee with the present invention. However, while the circuits described in this patent provide some intrinsic first order compensation for supply voltage variations, significantly greater compensation for such variations would be desirable.
U.S. Pat. No. 4,636,983, assigned to a common assignee with the present invention, describes a memory circuit (FIG. 6) which includes some compensation for process, temperature and supply variations which assist in proper sensing operation.